Please refer to FIG. 9, which is the cross-sectional schematic showing an embodiment of the backside metallization for compound semiconductors of conventional technology. The backside metallization for compound semiconductors of conventional technology comprises: a compound semiconductor substrate 90, a front-side metal layer 91, a backside metal layer 92, a diffusion barrier layer 93, a die attachment metal layer 94, a plurality of street recesses 95 and a plurality of substrate via holes 96. The compound semiconductor substrate 90 is made of SiC or GaN. The front-side metal layer 91 is formed on a top surface 902 of the compound semiconductor substrate 90. The plurality of substrate via holes 96 are formed by etching the compound semiconductor substrate 90 from a bottom surface 901 of the compound semiconductor substrate 90. Each of the substrate via holes 96 has an inner surface. The inner surface of the substrate via hole 96 includes a surrounding surface 961 and a top 962. The surrounding surface 961 of the inner surface of the substrate via hole 96 is defined by the compound semiconductor substrate 90. The top 962 of the inner surface of the substrate via hole 96 is defined by the front-side metal layer 91. The backside metal layer 92 is formed on the bottom surface 901 of the compound semiconductor substrate 90, the surrounding surface 961 of the inner surface of each of the substrate via holes 96 and the top 962 of the inner surface of each of the substrate via holes 96, such that the backside metal layer 92 and the front-side metal layer 91 are electrically connected at the top 962 of the inner surface of the substrate via hole 96. The backside metal layer 92 is made of Au. The backside metal layer 92 has an outer surface 921. The diffusion barrier layer 93 is formed on the outer surface 921 of the backside metal layer 92 of an adjacent area 97 of the substrate via hole 96 and the outer surface 921 of the backside metal layer 92 inside the substrate via hole 96. The diffusion barrier layer 93 is made of Al2O3, SiO2 or silicon nitride. The die attachment metal layer 94 is formed on the outer surface 921 of the backside metal layer 92 other than the adjacent area 97 of the substrate via hole 96 and other than the substrate via hole 96. The diffusion barrier layer 93 and the die attachment metal layer 94 are connected at an outer edge 971 of the adjacent area 97 of the substrate via hole 96. The die attachment metal layer 94 is made of AuSn alloy, wherein the composition of AuSn alloy has 80 percent Au by weight and 20 percent Sn by weight. The surrounding of the plurality of street recesses 95 is defined by the die attachment metal layer 94 and the backside metal layer 92. The top of the plurality of street recesses 95 is defined by the bottom surface 901 of the compound semiconductor substrate 90.
Please refer to FIG. 10, which is the cross-sectional schematic showing another embodiment of the backside metallization for compound semiconductors of conventional technology. Cutting the structure of the embodiment of FIG. 9 along the plurality of street recesses 95 may form a plurality of dies 9. FIG. 10 shows the structure of a single die 9. Forming an antioxidant layer 99 on a top surface of a leadframe 98. Positioning the die 9 on the antioxidant layer 99 of the leadframe 98. Applying a force downwardly from a top of the die 9 and heating the die 9 and the leadframe 98 (and the antioxidant layer 99) to between 280° C. and 320° C. Please also refer to FIG. 11, which is the Au—Sn binary phase diagram. Since the composition of the die attachment metal layer 94 is 80 percent Au by weight and 20 percent Sn by weight, when heating more than 278° C., a solid to liquid phase transition in the die attachment metal layer 94 is induced. Au and Sn of the die attachment metal layer 94 are melting mutually and then forming an AuSn alloy after cooling. Therefore, the die 9 is fixed on the antioxidant layer 99 of the leadframe 98 by the die attachment metal layer 94. The die attachment metal layer 94 has the function of electrical conducting and thermal conducting.
In conventional technology, the die attachment metal layer 94 (80 percent Au by weight and 20 percent Sn by weight) is formed on the outer surface 921 of the backside metal layer 92 (made of Au). Therefore, the Au of the backside metal layer 92 can easily diffuse into the die attachment metal layer 94 such that the Au of the composition of the die attachment metal layer 94 becomes more than 80 percent by weight. From the Au—Sn binary phase diagram, it is clear that when the ratio of the Au and Sn of the die attachment metal layer 94 has some changes in some local areas, especially when the percentage of Au by weight raises a little bit in some local areas, the temperature of solid to liquid phase transition of the die attachment metal layer 94 will raise dramatically in these local areas. Under the normal process temperature, the die attachment metal layer 94 in these local areas cannot transit to liquid phase since the heating temperature is not high enough so that some defects are formed in these local areas. These defects will cause poor electrical conductivity or poor thermal conductivity of the compound semiconductor devices. The efficiency of the compound semiconductor devices will be reduced such that the compound semiconductor devices cannot pass the reliability tests. Even further, the compound semiconductor devices will be harmful.
Furthermore, from the outer edge 971 of the adjacent area 97 of the substrate via hole 96, the die attachment metal layer 94 can migrate into the substrate via hole 96 between the backside metal layer 92 and the diffusion barrier layer 93. More seriously, the Sn of the die attachment metal layer 94 can migrate and diffuse into the top 962 of the inner surface of the substrate via hole 96 such that the Sn of the die attachment metal layer 94 contacts with the front-side metal layer 91. It will harm the compound semiconductor devices formed on the top surface 902 of the compound semiconductor substrate 90.
Moreover, please refer to the embodiment of FIG. 10, during the process of applying the force downwardly from the top of the die 9 and heating the die 9 and the leadframe 98 (and the antioxidant layer 99) to between 280° C. and 320° C. such that a solid to liquid phase transition in the die attachment metal layer 94 is induced. The die attachment metal layer 94 around the die 9 is squeezed out and forms a squeezed-out part 942 of the die attachment metal layer 94 as shown in FIG. 10. However, the squeezed-out part 942 of the die attachment metal layer 94 cannot be good adhered to the bottom surface 901 of the compound semiconductor substrate 90 (SiC substrate or GaN substrate). It is harmful to the structure strength of the squeezed-out part 942 of the die attachment metal layer 94 around the die 9.
Accordingly, the present invention has developed a new design which may avoid the above mentioned drawbacks, may significantly enhance the performance of the devices and may take into account economic considerations. Therefore, the present invention then has been invented.